verilog - Synthesis of wand as and gate -

verilog - Synthesis of wand as and gate -

here have multiple drivers 1-bit port x. want resolve using wand net type. when check out schematics, to the lowest degree important bit of input port connected port x, while remaining bits unread. want bits of a used , assign x port using , gate resolve multiple drivers.

module test(input [3:0]a, output [1:0]b); wire [3:0] d [1:0]; wand temp; assign temp=a; inst inst_name (.x(temp),.y(d[1][3]),.z(b[1:0])); assign d[1] = {4'd15}; assign d[0] = {4'd0}; endmodule module inst (input wand x,y, output [1:0]z); assign z={x,y}; endmodule

you can utilize for generate loop accomplish want:

generate for(i = 0; < 4; = + 1) begin: wand_loop assign temp = a[i]; end endgenerate

this code generate next structure:

edit: correctly pointed out @mcleod_ideafix, if define temp simple wire can utilize next assignment: assign temp = &a; accomplish goal.

verilog