vhdl - how to connect output signal of one module to input signal of other module -

vhdl - how to connect output signal of one module to input signal of other module -

suppose vhdl code this:

entity x1: port(a: out std_logic; .... .... ); architecture behv1 of x1 .... end behv1; entity y1 port(b: in std_logic; .... .... ); architecture behv1 of y1 begin m1: x1 port map(a=>b); end behv1;

so, here output signal of entity x1 whcih connected straight input b of other entity y1

you're kinda going in wrong way.

entity y1 provides interface of y1 entity. specifies have input entity, b. means can read value of b within architecture declaration. should implement want y1 module within architecture behav1.

from understand though, want instantiate x1 , y1, connect them together. this, need provide implementation of x1 , y1, , instantiate both in separate top-level , connect them together. this:

entity x1: port(a: out std_logic; .... .... ); architecture behv1 of x1 -- something... end behv1; entity y1 port(b: in std_logic; .... .... ); architecture behv1 of y1 begin -- something... end behv1; entity toplevel port ( clk : in std_logic; ... ); architecture toplevel_arch of toplevel signal x1_output : std_logic; -- temp connect both modules begin m_x1: x1 port map(a => x1_output); m_y1: y1 port map(b => x1_output); end toplevel_arch;

vhdl